1. Technical Field
The present invention relates generally to semiconductor manufacturing equipment and, more particularly, to an apparatus and method for inspecting overlay patterns in a semiconductor device.
A claim of priority is made to Korean Patent Application No. 10-2005-0120383, filed Dec. 9, 2005, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated herein by reference in its entirety.
2. Discussion of Related Art
To meet the increasing demand for semiconductor components having high operating speeds and small sizes, manufacturers have made improvements to the semiconductor manufacturing processes. The improvements in the semiconductor manufacturing processes have lead to increasing production yields from these processes.
While production yields of semiconductor components have improved, there is also a need for methods and equipment that may be used to inspect for manufacturing defects during the various semiconductor fabrication processes. The manufacturing defects may occur due to various reasons. For example, process conditions are frequently varied in a photolithographic process (one of the main semiconductor manufacturing process). These variations in process conditions may lead to manufacturing defects in the semiconductor components. It is therefore desirable to develop an inspection process for detecting manufacturing defects and an apparatus for performing the inspection process.
As mentioned above, the photolithographic process is an important semiconductor manufacturing process. The photolithographic process refers to a process of applying a photo-resist on a wafer and exposing and developing the photo-resist to form a photo-resist pattern. Then, either the wafer under the photo-resist pattern or a thin layer formed on the wafer is patterned using the photo-resist pattern as an etch mask.
An attempt may be made to form a precise semiconductor pattern on the wafer through the photolithographic process. At this time, in order to enable the photo-resist pattern to be formed in a desired shape, a “reticle” may be used as a pattern mask for selectively sensitizing the photo-resist. In order to produce a precise pattern, the reticle should be positioned at a designated position and the wafer corresponding to the reticle should also be aligned properly. However, the reticle and the wafer may not be aligned properly. This misalignment may be due to various reasons such as, for example, a malfunction in the optical system that propagates incident light projected onto the reticle. This misalignment of the reticle and/or the wafer may cause various problems such as, for example, an imprecise semiconductor pattern. Furthermore, the problem may be exacerbated during the formation of subsequent patterns on the wafer. For example, other thin layer patterns that are formed in subsequent processes may now not be formed at their designated positions. These defects formed on a semiconductor device during the semiconductor manufacturing process may affect the functionality of the semiconductor device.
In order to overcome this problem, almost all reticles used in the exposure process may be formed with alignment patterns and overlay patterns. Alignment and overlay patterns may be used for proper alignment of the wafer. Specifically, the alignment pattern is used to align the wafer so that the exposure during the photolithographic process is performed only on those portions of the wafer that require the exposure. The overlay pattern is used for inspecting whether the patterns formed in the photolithographic process in the precedent and subsequent processes are consistent with each other. In particular, the overlay patterns may be made to overlap each other or may be arranged at a constant interval in such a manner that the overlay patterns formed in the precedent process can be compared with those formed in the subsequent process whenever the reticles are changed.
An apparatus may be used to inspect the overlay patterns and determine differences between the overlay patterns formed in different processes. The determined differences may be presented to an operator or a controller of the semiconductor manufacturing equipment. Based on the information received, the controller or operator may adjust the manufacturing equipment so that a photo-resist pattern is formed at a desired position.
At this time, the plurality of overlay patterns that are measured by the overlay pattern inspecting apparatus are formed one at a time, i.e., each overlay pattern is formed whenever one layer is formed on the wafer. Therefore, like the layers formed on the wafer, the overlay patterns are stacked over each other and consequently, are not located on the same plane.
The conventional overlay pattern inspecting apparatus is configured to magnify and project a plurality of neighboring overlay patterns through an optical module. Furthermore the apparatus shoots the magnified and projected overlay patterns at a pickup unit such as a camera, and obtains image signals corresponding to the plurality of overlay patterns. Furthermore, a readout unit in the apparatus converts the image signals obtained at the pickup unit into images, reads out a positional difference between the plurality of overlay pattern images corresponding to the plurality of overlay patterns, calculates a correction value for the overlay patterns, and feeds the result to an exposure apparatus.
Specifically, in a conventional overlay pattern inspecting apparatus, the optical module irradiates incident light made up of white visible light onto a wafer, magnifies and projects the reflected light, and enables the pickup unit to obtain images of the plurality of overlay patterns. Furthermore, the plurality of overlay patterns may be formed as recessed trenches or protruding blocks having a predetermined step height corresponding to the layer formed on the wafer.
While the conventional overlay pattern inspecting apparatus may be used to inspect overlay patterns, it has several shortcomings. For example, foreign materials such as slurry may be adhered in the trench or around the block. These foreign materials may be introduced by one or more manufacturing processes such as, for example, a proceeding planarization process, such as CMP (Chemical Mechanical Planarization.) This formation of foreign materials may distort a line width of the overlay patterns. Therefore, the visible light may be diffracted or scattered in a part of the overlay pattern which has a line width having a magnitude similar to a wavelength of the visible light. The scattering or diffraction of the visible light may cause incorrect overlay pattern inspection. For example, light made up of white visible light may be incident on the plurality of overlay patterns and may be subject to diffraction or scattering. This diffraction or scattering may cause the light to be reflected back with at least one of red, blue, and green colors.
In a conventional inspection apparatus, the pickup unit processes the reflected light which is diffracted or scattered by the overlay patterns into an image signal without change, thus distorting overlay pattern images in whole or in part. Furthermore, the pickup unit transmits these distorted images to the readout unit. As such, the readout unit may incorrectly calculate the correction value for the overlay patterns on the basis of the plurality of overlay pattern images that are distorted in whole or in part. This incorrect calculation may lead to faulty fabrication of the semiconductor devices, thus resulting in the decrease of a production yield of semiconductor devices.
In addition, the overlay patterns are generally formed on the wafer so as to be symmetrical about their center in the vertical and horizontal directions. However, when some of the overlay patterns are damaged or asymmetrical, the readout unit may fail to correctly calculate the correction value for the overlay patterns on the basis of the image signals of the overlay patterns that are picked up at the pickup unit. This type of incorrect calculation of the correction value may also result in the decrease of a production yield of semiconductor devices.
The present disclosure is directed to overcoming one or more of the problems associated with the prior art overlay pattern inspecting apparatus.